If the clocked output isn't "LOCKED" , should a new reset signal be sent every clock cycle? I've used the enable counter to provide a delay between successive reset pulses i.e(give clock manager time to lock)? And a shift register to make the rst_in to last 3 seconds.
P.S. Is this the right way to reset a DCM? Wouldn't it be better if I tied the DCM 'rst_in' to the external reset? assign rst_in = RESET (From FPGA button)?
Have you read UG382, namely the sections titled "Using the LOCKED Signal" and "RST Input Behavior"?
In summary you should reset when there is a high->low transition on LOCKED and when either of the non-sticky status[2] or status[0] bits get set (means the clocks stopped).
Your "enable" bothers me as it looks like a potential dead lock condition as it could force a new reset (with a start of a new lock acquire) if the DCM is slow to lock on the clock (maybe the clock has excessive jitter.
I also have an issue with using the logical ! (not) operator on a bus (!enable). The logical operators are defined for use on single bits not buses. Using the correct reduction NOR operation is preferred for detection a bus is 0, i.e. ~|enable. This lets another reader of your code understand the intent better.
I also don't understand how this is supposed to result in 3 clocks of SR...
Code:
SR[0] <= 1;
SR <= SR >> 1;
assign rst_in = (SR[2] | SR[1] | SR[0]); //assert reset for 3 clock cyles
How is a right shift supposed to do anything SR[2:1] are never 1. You could have also used a reduction OR instead of writing out all the bits.
Code:
assign rst_in = |SR;
Your code may also result in multiple drivers when compiling it as SR is driven by two different always blocks. I always avoid this type of coding style as it may give different results depending on the tool.
reg LOCKED_R;
reg [3 : 0] SR;
always @ (posedge CLKIN)
begin
if(RESET)
begin
SR [3 : 0] <= 4'b111;
LOCKED_R <=0;
end
else
begin
LOCKED_R <= LOCKED;
if(LOCKED < LOCKED_R | STATUS [1] ) // H to L on LOCKED | CLKIN UNSTABLE
SR <= {1'b1 , SR[3 : 1]};
else
SR <= {1'b0 , SR[3 : 1]};
end
end
assign rst_in = ( (SR[2] | SR[1] | SR[0]) || RESET);
Now, I am not sure about how to implement reset for all the other registers in the design, since they are driven by the DCM clock output.
If the RESET signal pulse lasts for a period shorter than what it takes to assert the locked signal, (which probably will be the case because of the OR gate at the rst_in), the registers will never be reset.
Code:
always @ (posedge clk)
begin
if (LOCKED && !STATUS[1])
begin
//GOOD TO GO
end
else
begin
//RESET
end
end
Does the always @ (posedge clk) trigger even when (LOCKED && !STATUS[1]) isn't high? If so, why does the simulation show everything inactive until the locked bit doesn't go high?
Will I have to use an async RESET to reset my registers?