ok , this is my layout for 8 transistor using L-edit
after exporting the file to T-spice for simulation , I got this message :
T-Spice - Tanner SPICE
T-Spice - Tanner SPICE
Version 14.11
Network license
Product Release ID: T-Spice Win32 14.11.20090811.05:10:58
Copyright © 1988-2009 Tanner EDA
Parsing "C:\Users\LOLYPOP\Desktop\XOR2-mod-1.spc"
Warning : gmin value (0) is less than pivtol (1e-014)
Loaded MOSLevel2 model library, SPICE Level 2 MOSFET revision 1.0
Warning : Pulse period is too small, reset to rt + ft + pw = 1.008e-007
Accuracy and Convergence options:
cshunt = 0 [F] dcstep = 0.2 gmin = 0 [mhos]
General options:
threads = 2
Device and node counts:
MOSFETs - 6 MOSFET geometries - 5
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 4 Boundary nodes - 5
Total nodes - 9
*** 2 WARNING MESSAGES GENERATED DURING SETUP
Opening output file "C:\Users\LOLYPOP\Desktop\XOR2-mod-1_20110529_192842\XOR2-mod-1.out"
Opening output file "C:\Users\LOLYPOP\Desktop\XOR2-mod-1_20110529_192842\XOR2-mod-1.dat"
Conventional DC operating point computation failed.
Gmin stepping failed
Final gmin value = 1e-006, dcstep = 0.2
Source stepping failed at 0.00% rampup
Multi-rate source stepping failed at 0.00% rampup
Pseudotransient analysis at 0% completion
Pseudotransient analysis failed
Fatal Error : DC operating point non-convergence
Parsing 0.01 seconds
Setup 0.09 seconds
DC operating point 0.14 seconds
Transient Analysis 0.00 seconds
Overhead 0.13 seconds
-----------------------------------------
Total 0.37 seconds
Simulation failed with 2 Warnings 1 Fatal Error
The T-spice file for thi simulation was :
*******************************************************************************
* SPICE netlist generated by HiPer Verify's NetList Extractor
*
* Extract Date/Time: Sat May 28 23:18:59 2011
* L-Edit Version: L-Edit Win32 14.11.20090811.09:15:20
*
* Rule Set Name:
* TDB File Name: C:\Users\LOLYPOP\Desktop\3-XOR.tdb
* Command File: C:\Users\LOLYPOP\Desktop\l-edit student version 72last\mosis\mhp_ns5.ext
* Cell Name: XOR2-mod-1
* Write Flat: NO
********************************************************************************
****************************************
M1 1 VA VSS VSS NMOS l=5e-007 w=1.5e-006 ad=2.625e-012 as=3.375e-012 pd=6.5e-006 ps=7.5e-006 $ (-4.75 3.875 -4.25 5.375)
M2 Vout 1 VSS VSS NMOS l=5e-007 w=1.5e-006 ad=2.625e-012 as=3.375e-012 pd=6.5e-006 ps=7.5e-006 $ (20 3.875 20.5 5.375)
M3 1 VC VA 2 PMOS l=5e-007 w=3.25e-006 ad=6.09375e-012 as=6.5e-012 pd=1.025e-005 ps=1.05e-005 $ (-14.125 11.25 -13.625 14.5)
M4 1 VA VC 2 PMOS l=5e-007 w=3.125e-006 ad=5.46875e-012 as=7.03125e-012 pd=9.75e-006 ps=1.075e-005 $ (-4.75 11.375 -4.25 14.5)
M5 Vout VB 1 3 PMOS l=5e-007 w=3.375e-006 ad=6.32813e-012 as=6.75e-012 pd=1.05e-005 ps=1.075e-005 $ (10.625 11.125 11.125 14.5)
M6 Vout 1 VB 3 PMOS l=5e-007 w=3.375e-006 ad=5.90625*e-012 as=7.59375e-012 pd=1.025e-005 ps=1.125e-005 $ (20 11.125 20.5 14.5)
VSS VSS 0 DC 0
VB VB 0 Pulse ( 0 3 1p 1p 1p 1n 2n)
VA VA 0 Pulse ( 0 3 1p 0.1n 1p 0.75n 1.5n)
VC VC 0 Pulse ( 0 3 1p 0.1u 1p 0.75n 1.5n)
.options dcstep =0.2
.options cshunt = 0
.options gmin = 0
.TRAN .1n 4n
.probe
of course I added the Mosfet model in the end
Can anybody help me , please ?!!