# Digital circuit layout and simulation

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#### lolypop

##### Newbie level 5
Hello ,
I Have been trying to draw the layout of a full adder using first the usual 28 Transistor full adder and then tried to simulate it using 8 transistor full adder
I faced many problems in the second circuit but what got me stuck is that after testing the New Xor layout alone and then combine two Xor with a Mux to simulate the full adder I got the following Error :
Conventional DC operating point computation failed.
Gmin stepping failed
Final gmin value = 1e-006, dcstep = 0.2
Source stepping failed at 0.00% rampup
Multi-rate source stepping failed at 0.00% rampup
Pseudotransient analysis at 0% completion
Pseudotransient analysis failed
Fatal Error : DC operating point non-convergence

Can somebody help me resolve this problem I tried everything I know to fix the problem but it didn't work

I also have a Question regarding the simulation of power sonsumtion in full adder how can I do it using either T-spice or PSpice . Does Anybody know ??

Please I really need an answer , If you have any idea please reply to my post . I'm in dire need for some help .

Thank you

#### dgnani

There is not much to go after, my best guess is that you have something floating say the body of a transistor, if you want a better guess provide some more details

#### lolypop

##### Newbie level 5
ok , this is my layout for 8 transistor using L-edit

after exporting the file to T-spice for simulation , I got this message :
T-Spice - Tanner SPICE
T-Spice - Tanner SPICE
Version 14.11
Product Release ID: T-Spice Win32 14.11.20090811.05:10:58

Parsing "C:\Users\LOLYPOP\Desktop\XOR2-mod-1.spc"
Warning : gmin value (0) is less than pivtol (1e-014)
Loaded MOSLevel2 model library, SPICE Level 2 MOSFET revision 1.0
Warning : Pulse period is too small, reset to rt + ft + pw = 1.008e-007

Accuracy and Convergence options:
cshunt = 0 [F] dcstep = 0.2 gmin = 0 [mhos]

General options:

Device and node counts:
MOSFETs - 6 MOSFET geometries - 5
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 4 Boundary nodes - 5
Total nodes - 9

*** 2 WARNING MESSAGES GENERATED DURING SETUP

Opening output file "C:\Users\LOLYPOP\Desktop\XOR2-mod-1_20110529_192842\XOR2-mod-1.out"
Opening output file "C:\Users\LOLYPOP\Desktop\XOR2-mod-1_20110529_192842\XOR2-mod-1.dat"
Conventional DC operating point computation failed.
Gmin stepping failed
Final gmin value = 1e-006, dcstep = 0.2
Source stepping failed at 0.00% rampup
Multi-rate source stepping failed at 0.00% rampup
Pseudotransient analysis at 0% completion
Pseudotransient analysis failed
Fatal Error : DC operating point non-convergence

Parsing 0.01 seconds
Setup 0.09 seconds
DC operating point 0.14 seconds
Transient Analysis 0.00 seconds
-----------------------------------------
Total 0.37 seconds

Simulation failed with 2 Warnings 1 Fatal Error

The T-spice file for thi simulation was :
*******************************************************************************
* SPICE netlist generated by HiPer Verify's NetList Extractor
*
* Extract Date/Time: Sat May 28 23:18:59 2011
* L-Edit Version: L-Edit Win32 14.11.20090811.09:15:20
*
* Rule Set Name:
* TDB File Name: C:\Users\LOLYPOP\Desktop\3-XOR.tdb
* Command File: C:\Users\LOLYPOP\Desktop\l-edit student version 72last\mosis\mhp_ns5.ext
* Cell Name: XOR2-mod-1
* Write Flat: NO
********************************************************************************

****************************************

M1 1 VA VSS VSS NMOS l=5e-007 w=1.5e-006 ad=2.625e-012 as=3.375e-012 pd=6.5e-006 ps=7.5e-006 $(-4.75 3.875 -4.25 5.375) M2 Vout 1 VSS VSS NMOS l=5e-007 w=1.5e-006 ad=2.625e-012 as=3.375e-012 pd=6.5e-006 ps=7.5e-006$ (20 3.875 20.5 5.375)
M3 1 VC VA 2 PMOS l=5e-007 w=3.25e-006 ad=6.09375e-012 as=6.5e-012 pd=1.025e-005 ps=1.05e-005 $(-14.125 11.25 -13.625 14.5) M4 1 VA VC 2 PMOS l=5e-007 w=3.125e-006 ad=5.46875e-012 as=7.03125e-012 pd=9.75e-006 ps=1.075e-005$ (-4.75 11.375 -4.25 14.5)
M5 Vout VB 1 3 PMOS l=5e-007 w=3.375e-006 ad=6.32813e-012 as=6.75e-012 pd=1.05e-005 ps=1.075e-005 $(10.625 11.125 11.125 14.5) M6 Vout 1 VB 3 PMOS l=5e-007 w=3.375e-006 ad=5.90625*e-012 as=7.59375e-012 pd=1.025e-005 ps=1.125e-005$ (20 11.125 20.5 14.5)

VSS VSS 0 DC 0

VB VB 0 Pulse ( 0 3 1p 1p 1p 1n 2n)

VA VA 0 Pulse ( 0 3 1p 0.1n 1p 0.75n 1.5n)
VC VC 0 Pulse ( 0 3 1p 0.1u 1p 0.75n 1.5n)
.options dcstep =0.2
.options cshunt = 0
.options gmin = 0

.TRAN .1n 4n
.probe

of course I added the Mosfet model in the end

Can anybody help me , please ?!!

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#### dgnani

Assuming TSPICE uses the usual SPICE convention the order of pin in a MOSFET is
D G S B
This being a digital circuit I would expect
- the S B of all NMOS to be shorted to VSS (which is the case)
- the S B of all PMOS to be shorted to VDD, which is not the case and I do not even see among your sources...

If you still have difficulties post a clearer image of your layout:
- larger
- make labels legible
- lose the grid dots

#### lolypop

##### Newbie level 5
Ok , maybe this is the problem , only the bulk of PMOS and NMOS transistor are connected to VDD and VSS resopectively while the sources are connected to the input as in pseudo NMOS and transmission gate circuit . the odd thing is when I simulate each gate alone it will work perfectly well but when combined together it give the fatal error worning .

I have attached a zip file in it the design I'm using

Thank you so much for your replies

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#### dgnani

comparing your design schematic to the netlist I see the following:
- there are only 6 MOSFETs (the 2-FET MUX is missing)
- the PMOS bodies are not connected to VDD but floating on two separate nets (named 2 and 3)
- in your netlist you do not have a voltage source to bias this node -once they are together
- node B and Cout are swapped

Is this an extracted netlist?
Did you run LVS against a schematic view?

I did not study your layout in depth but I see 11 MOSFETs in there (there are 3 XORs)

#### lolypop

##### Newbie level 5
Ok , you are right , I didn't notice that when I tried to find a solution I started changing in the cells belong to the instance cell I attached in this post and ended with 3 XOR instead of one as for the bodies of NMOS nad PMOS transistors I did connected them to VDD and VSS represented by the long Metal one line in the top and bottom of each cell . I was able to simulate (XOR and 2-1 Mux layout alone without the second XOR ) Idon't know why every time I added it to the layout the Tspice give me the fatal error warning and stop the simulation .

AS for LVS to check my design , we didn't use LVS before is there any tutorial I could read to be able to use . I'd be forever thankful for your help

Regards

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#### dgnani

if you could post the netlist for the simulation of the actual layout we can proceed debugging

As of LVS I never used L-edit so I would not be able to help much there: what LVS tools do you have available?

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