Hi:Hi,
I recommend to be more exact in your naming the signals.
There are some issues, I'm not sure whether you want it this way or not.
Your "283" has inputs A0...A3, B0...B3 like in the datasheet
But it has S1...S4, while the datasheet says S0..S3.
Usually the number is the bit number, so input bit 0 leads to output bit 0. Not in your case.
Usually S0 is the least significant bit.
On the right bottom corner the result is totally confused.
Usually it should be in the order : D7-D6-D5-D4-D3-D2-D1-D0
(while D7 : D4 should be the outputs S3 : S0 of the higher nibble '283')
But in your case output is drawn in the order: D0-D1-D2-D3-D7-D6-D5-D4 (the right most bit (D4) is marked as 'LSB')
Klaus
Without knowing the exact timing of clocks and gate pulses, we can't determine if it's correct to see 15 and 31 or 16 and 32 final counts. We also don't know how the adder result is latched. For the time being I'll assume we see just normal operation. You get out what you put in.
So the 01111111 must be the actual sum produced by the adders. The question that remains is why the sum is wrong?Hi and thank you for trying to be helpful to me:
I was first testing with 163 counter but I had the same wrong readings at the output of the adder. So I decided to see what happens if I use the 4040. The sum is wrong with both counters.
And I do have a count, pause and reset pulses. I AND gate the clocks with the time base so that when timebase is logic low no clock input is fed to the counters and the counters pause. I also create a pulse (let’s call is pulse-1) right before the reset pulse is generated. So that the two shoulder to shoulder pulses (pulse-1 and reset pulse) of the same length are generate during the low logic of the time base. The pulse-1 provides plenty of time for capturing the output of the adder when using the oscilloscope.
I am not too concerned about the count of 31 and 32 for example as that is solved with synchronous. But I do see variations at t each of the outputs of the adder as a series of pulses at each pin. When I feed the negative of the scope with the reset pulse, I see between 1 and 4 pulses at the outputs. And the sum output is 00111111.
When i feed the negative of the scope with the pulse-1, I see more pulse cycles at each of the output pins because the pulse-1 provides more time to capture outputs. And in this case I see output 01111111.
I just realized that when I verified the outputs during the entire pause time (the time that the low time base last) instead of just during the pulse-1 time, the actual output is all ones as 11111111.Hi and thank you for trying to be helpful to me:
I was first testing with 163 counter but I had the same wrong readings at the output of the adder. So I decided to see what happens if I use the 4040. The sum is wrong with both counters.
And I do have a count, pause and reset pulses. I AND gate the clocks with the time base so that when timebase is logic low no clock input is fed to the counters and the counters pause. I also create a pulse (let’s call is pulse-1) right before the reset pulse is generated. So that the two shoulder to shoulder pulses (pulse-1 and reset pulse) of the same length are generate during the low logic of the time base. The pulse-1 provides plenty of time for capturing the output of the adder when using the oscilloscope.
I am not too concerned about the count of 31 and 32 for example as that is solved with synchronous. But I do see variations at t each of the outputs of the adder as a series of pulses at each pin. When I feed the negative of the scope with the reset pulse, I see between 1 and 4 pulses at the outputs. And the sum output is 00111111.
When i feed the negative of the scope with the pulse-1, I see more pulse cycles at each of the output pins because the pulse-1 provides more time to capture outputs. And in this case I see output 01111111.
--- Updated ---
So the 01111111 must be the actual sum produced by the adders. The question that remains is why the sum is wrong?
Hi:Hi,
I can't follow your textual descriptions.
Klaus
I will try the manual clocking to see the results.give one counter one clock pulse - NOT a string of 512 Hz, not a string of 1024 Hz - just one clock pulse to one counter
then measure all of the A inputs to the adder - report it as a binary number
then measure all of the B inputs to the adder - report it as a binary number
then measure all of the S outputs of the adder - report is as a binary number
then give that same counter about 75 pulses and give the other counter about 100 pulses
repeat the measurements and report the results
then give that same counter another 75 pulses and give the other counter another 100 pulses
repeat the measurements and report the results
the goal here is to ensure the correct wiring and operation of the adder
once that's verified, the timing questions will need to be addressed
how are you determining the binary numbers you are reporting?
The 74HC283 has pins numbered A4-A1 and B4-B1 with the output on S4-S1, so the output is marked correctly and the inputs are incorrectly marked.Hi,
I recommend to be more exact in your naming the signals.
There are some issues, I'm not sure whether you want it this way or not.
Your "283" has inputs A0...A3, B0...B3 like in the datasheet
But it has S1...S4, while the datasheet says S0..S3.
Usually the number is the bit number, so input bit 0 leads to output bit 0. Not in your case.
Usually S0 is the least significant bit.
On the right bottom corner the result is totally confused.
Usually it should be in the order : D7-D6-D5-D4-D3-D2-D1-D0
(while D7 : D4 should be the outputs S3 : S0 of the higher nibble '283')
But in your case output is drawn in the order: D0-D1-D2-D3-D7-D6-D5-D4 (the right most bit (D4) is marked as 'LSB')
Klaus
Thank you for your analysis of the problem.The 74HC283 has pins numbered A4-A1 and B4-B1 with the output on S4-S1, so the output is marked correctly and the inputs are incorrectly marked.
It would be better if you showed us a real schematic that has the pin numbers along with the pin names, but I suspect you don't have a real schematic just a Visio (or similar) drawing.
I think you should just report the logic levels on the pins of each part.
In order of most likely issue to least likely issue
1. Wiring problem (pin number/pin name mismatch, incorrect handling of ci/co, etc)
2. Timing problem (glitches in the clock generation from gating, not enough settling time)
3. Measurement errors (may be caused by incorrectly drawn schematic)
4. Part failures (then again if these parts are old and have been handled a lot with no ESD precautions then this might be #1)
I am already in process of disconnection everything. Perhaps this will continue in the future.Hi,
a schematic is a good information what you want to do.
But a photo is good information how it really is.
Klaus
Did you use bypass capacitors (from VCC to GND) on the supply pins of all the ICs? If you don't have enough bypass you can see issues with current and voltage fluctuations on your power supply. The bypass capacitors are used to supply enough transient current when the ICs switch. From your description you probably don't have enough (or any) bypass.Another thing that is perhaps unusual is that when the counters and the adder function together, my power supply shows fast variations in the current and power consumption of the circuit. (1) Should I consider that as normal?
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