Differential clock is mainly used for reducing the Noise immunity. So in that sense we can use the differential clock in the DDR side, because most of the cases the DDR are working at high frequency. Noises are more come in to picture when we are working with high frequencies.
When we are using a differential clock there will be two io ports for the same signal (one positive and one negative), one is the inversion of the other. so the when one is at level high , then the other will be at level low, the data is sampled only when both the clock signals are at exact opposite condition, which will reduce the immunity.
For increasing the transition speed most of the design we are using the differential signals in 2.5V (LVDS2.5, lvcmos2.5,etc)