Differential clocking

[spman]

Hi,

I know somewhat about differential signaling and use of it to overcome noise...
But i don't know anything about differential clock and it's utilization. Would anyone please tell me how it is useful?
For example for DDR RAM.

Thanks

 

[joelby]

There's nothing particularly special about the differential clock used in DDR memory compared with other applications. Are you confusing differential-ism with double data rate? DDR means that data is transferred on both the rising and falling edges of the clock, rather than at a single edge only.

If this isn't what you meant, please let us know.

 

[spman]

Why differential clock is used? What occurs if we replace it with single ended clock?

 

[joelby]

For all the same reasons as differential signalling such as better noise immunity. If your device only accepts a differential clock, then a single ended clock might not work at all.

 

[spman]

Thank you joelby.

Another question that i'm not sure if it is related to this topic !
How is it possible to transfer data on both the rising and falling edges of the clock? Does differential clock help the device transfer in double data rate manner besides noise immunity capability? Or the internal clock of the device is twice the differential clock?

 

[joelby]

A D flip flop is sensitive to one edge only, so you need to use two flip flops, one with an inverted clock. This will produce two output bits for every clock period. Alternatively you can use a clock at twice the frequency (and with matched phase) and use a normal flip flop.

Differential clocks don't really help with DDR on its own, though you could imagine ways that a chip designer could more easily recover two 180 degree clocks from a differential clock input.

In my experience with Xilinx FPGAs, you convert both single ended and differential clocks to single ended internal clocks and they're otherwise treated identically. For DDR outputs they support both clock inversion and 180 degree global clocks.

 

[naught]

It is recommended to use differential clocks for high frequencies. As a rule of thumb, high frequency is generally considered to be above 100MHz. The main advantage of differential clocks over single-ended counterparts is common-mode noise rejection, which provides better noise immunity. Differential clocks with PECL, LVPECL, and LVDS signal levels are popular choices to clock high-speed logic.
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the above comes from the following reference.
Stavinov, Evgeni (2011-05-18 00:00:00+08:00). 100 Power Tips for FPGA Designers (Kindle Locations 1487-1490). OutputLogic.com. Kindle Edition.

 

[ads_ee]

You know that most of those differential clocks on RAMs aren't differential they are positive and negative clocks where the rising edge of the two clocks are used to capture the two phases of the DDR data. I don't beleive the rational for making them psudo-differential is to improve noise immunity, but it's instead to improve the capture of the DDR data using two different rising edge clocks that are 180 degrees out of phase instead of trying to use the negative edge of a single ended clock.

 

[spman]

Yes. I had doubted to it. so Which is correct? Noise immunity or DDR capturing?

But there is another ambiguity. Doesn't differential clock identical to positive and negative clocks?

 

[joelby]

Yes. I had doubted to it. so Which is correct? Noise immunity or DDR capturing?

Can't it be both? And does it matter?

But there is another ambiguity. Doesn't differential clock identical to positive and negative clocks?

Technically yes, but what sort of clock do you mean? Typically differential I/Os will use a signalling standard such as LVDS or SSTL_18, which specify common mode voltages, characteristic impedance, termination requirements, etc.

 

[imbichie]

Differential clock is mainly used for reducing the Noise immunity. So in that sense we can use the differential clock in the DDR side, because most of the cases the DDR are working at high frequency. Noises are more come in to picture when we are working with high frequencies.

When we are using a differential clock there will be two io ports for the same signal (one positive and one negative), one is the inversion of the other. so the when one is at level high , then the other will be at level low, the data is sampled only when both the clock signals are at exact opposite condition, which will reduce the immunity.

For increasing the transition speed most of the design we are using the differential signals in 2.5V (LVDS2.5, lvcmos2.5,etc)

 

[spman]

What advantage will have the differential clock for the DDR RAMs when other signals are simply single-ended? Only the clock has noise immunity! If there is any noise disturbing clock, also it can destroy other signals such as data signals that can change at high frequency. doesn't it?

 

[ads_ee]

In the case of the inverted clocks for RAMs there isn't any differential signalling involved. They only look differential because they are named something like C and C_bar. The two clocks themselves typically use some low voltage single ended standard such as HSTL-I/II/III or SSTL-I/II/III.

If you treat those clocks as differential when routing the board you may actually cause problems as they aren't differential and the cross talk between the two lines is likely to result in problems with writing to the RAM.

As I stated before the reason for having two separate clocks is to allow for more precise alignment of the rising edges of the clock with the data. Clocks are notoriously bad at having 50% duty cycles. So if you use a non 50% duty cycle you're going to eat into your timing budget on one of the two edges. By using two clocks that are 180 degrees out of phase you use the rising edge of both clocks and ensure you have the full width (half the clock period) of the eye to play around with capturing the data.

 

[spman]

In the case of the inverted clocks for RAMs there isn't any differential signalling involved. They only look differential because they are named something like C and C_bar. The two clocks themselves typically use some low voltage single ended standard such as HSTL-I/II/III or SSTL-I/II/III.

If you treat those clocks as differential when routing the board you may actually cause problems as they aren't differential and the cross talk between the two lines is likely to result in problems with writing to the RAM.

As I stated before the reason for having two separate clocks is to allow for more precise alignment of the rising edges of the clock with the data. Clocks are notoriously bad at having 50% duty cycles. So if you use a non 50% duty cycle you're going to eat into your timing budget on one of the two edges. By using two clocks that are 180 degrees out of phase you use the rising edge of both clocks and ensure you have the full width (half the clock period) of the eye to play around with capturing the data.

Very nice ! Thanks a lot