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How exactly does differential signal lead to low power consumption in FPGAs?

matrixofdynamism

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Differential signals use two lines instead of one. This means twice the switching activity compared with use of single ended transmission. How then does use of differential signalling achieve lower power in FPGAs since power dissipation mainly occurs when output is switching state?

Also, do FPGAs have real differential buffers inside or always use "emulated differential signals"?

Finally, shouldn't the use of termination resistors always lead to higher power dissipation relative to single ended signals for the same application since the termination resistors will always be sinking current to the ground?
 

KlausST

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Hi,

1) Where did you read that differential signalling leads to low power? Give us a link to the document, so we can read the context and discuss about it.

2) If i wanted to know this I´d read some FPGA datasheets .. form different families and different manufacturers.

3) I´m not sure if I correctly understand what you mean.
* differential signals usually are not terminated to GND. They are terminated against each other.
* signe ended signals may be terminated to GND, but not always.

****
Generally I don´t think differential signalling leads to lower power.
* The key is that they generate less EMI.
* They generate (ideally) no GND current in signal cables.
* The signal levels relate to each other and thus compensate for GND bounce.
* They use signal cables with matching characteristic impedance to avoid echo/ringing. ... thus are able for higher data rates.

But there are various differential signal interfaces. RS485, RS422, but also LVDS. LVDS works with much lower signal levels, thus the power dissipation in the termination resistors is reduced.

Klaus
 

dpaul

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@matrixofdynamism ,
After a long time with your generic questions..................

@KlausST ,
From statistics and history you might remember that the user @matrixofdynamism, is used to asking generic questions, many of which can be answered self reading of related materials.
So I generally care less for his posts!
 

matrixofdynamism

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As far as I am aware, when we need low power we use some type of differential signalling. By termination I mean termination resistors.

I have to do a lot of things as I am basically solo person, if I could just find answers through reading quickly then there is no need to post these questions.

The main question is, for a battery powered device that has an FPGA connected to high speed ADC, would using LVDS lead to lower power than using single ended CMOS?
 

KlausST

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Hi
As far as I am aware, when we need low power we use some type of differential signalling.
Again: where do you have this information from?

By termination I mean termination resistors.
This was not the question. The question is: where/how do you connect them.

The main question is, for a battery powered device that has an FPGA connected to high speed ADC, would using LVDS lead to lower power than using single ended CMOS?
I´ve already given general answers. For details you need to read the datasheets.
I wonder whether
* your ADC supports both LVDS and LVCMOS levels.
* how long the traces are from FPGA to ADC ...thus whether you need parallel termination at all
* what´s the expected data rate

Klaus
 

FlyingDutch

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Hello,

differential signal (like for example LVDS) use lover voltages Quaotation from wikipedia:

The low differential voltage, about 350 mV, causes LVDS to consume very little power compared to other signaling technologies. At 2.5 V supply voltage the power to drive 3.5 mA becomes 8.75 mW, compared to the 90 mW dissipated by the load resistor for an RS-422 signal.
See that link:
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling

Best Regards
 

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