Different timing behavior in RTL & Gate Level netlist simulation (using Cadence irun)
Hi, considering RTL code as below, at time=100(ns), A is forced to 1'b1.
a) In RTL (zero-delay-mode) simulation, I am able to see A2 becomes 1'b1 at positive clock edge at 100ns.
b) however, in Gate level (post-synthesis) (zero-delay-mode) simulation, I am not able to see A2 becomes 1'b1 at positive clock edge at 100ns.
Anyone may help to explain why? Thanks!
module block1 (A, B, A1) begin
input A, B;
output A1;
assign A1 = A & B;
endmodule
module top (clk, A, B, A2) begin
input clk,A,B;
output A2;
block1 block1_inst (.A(A), .B(B), .A1(A1));
always @ (posedge clk) begin
A2 <= A1;
end
initial #100 force A=1'b1
endmodule