Different timing behavior in RTL & Gate Level netlist simulation (using Cadence irun)

[childs72]

Different timing behavior in RTL & Gate Level netlist simulation (using Cadence irun)

Hi, considering RTL code as below, at time=100(ns), A is forced to 1'b1.
a) In RTL (zero-delay-mode) simulation, I am able to see A2 becomes 1'b1 at positive clock edge at 100ns.
b) however, in Gate level (post-synthesis) (zero-delay-mode) simulation, I am not able to see A2 becomes 1'b1 at positive clock edge at 100ns.
Anyone may help to explain why? Thanks!

module block1 (A, B, A1) begin

input A, B;
output A1;
assign A1 = A & B;​

endmodule

module top (clk, A, B, A2) begin

input clk,A,B;
output A2;
block1 block1_inst (.A(A), .B(B), .A1(A1));
always @ (posedge clk) begin
A2 <= A1;
end
initial #100 force A=1'b1​

endmodule

 

[sharath666]

Re: Different timing behavior in RTL & Gate Level netlist simulation (using Cadence i

The initial statement is not synthesizable. The synthesis toll will just ignore it. That is the reason.

 

[childs72]

Re: Different timing behavior in RTL & Gate Level netlist simulation (using Cadence i

Sorry let me produce a better example codes (the code here is only to illustrate the scenario, which is too much code to put here). The simulation is run with DUT before & after synthesis. Thx.

module block1 (A, B, A1) begin
input A, B;
output A1;
assign A1 = A & B;
endmodule

module DUT (clk, A, B, A2) begin
input clk,A,B;
output A2;
block1 block1_inst (.A(A), .B(B), .A1(A1));
always @ (posedge clk) begin
A2 <= A1;
end
endmodule

module testbench () begin
wire clk, A, B, A2;
DUT DUT (.clk(clk), .A(A), .B(B), .A2(A2));
always #20 clk <= ~clk;
assign A = 1'b0;
assign B = 1'b1;

initial #100 force A=1'b1

endmodule

 

[sharath666]

Re: Different timing behavior in RTL & Gate Level netlist simulation (using Cadence i

I don't think you understood what I said. I said that the initial statement is not synthesizable. Along with that the #100 delay is also not synthesizable. So you will see the #100 delay post synthesis.

 

[childs72]

Re: Different timing behavior in RTL & Gate Level netlist simulation (using Cadence i

I don't think you understood what I said. I said that the initial statement is not synthesizable. Along with that the #100 delay is also not synthesizable. So you will see the #100 delay post synthesis.

Sorry I should had explain in details to avoid the misunderstanding. In my case, DUT & block1 modules are in 1 verilog file; meanwhile testbench module is another verilog file.
for RTL simulation, I simulated using both verilog file as source files.
for Gate Level simulation, I synthesize DUT & block1 modules, then simulated using testbench verilog file & DUT post-synthesis gate level netlist (which is also a .v file somehow).

In my RTL (pre-synthesis) simulation, at 100ns, I can see A forced to 1'b1 and A1 becomes 1'b1 too. And A2 becomes 1'b1 at the rising clock edge at 100ns.
In my Gate (post-synthesis) simulation, at 100ns, I can see A forced to 1'b1 and A1 becomes 1'b1 too. But A2 does not change to 1'b1 at the rising clock edge at 100ns.

I understood what you said but that is not what I encountered.

Thanks.

 

[sharath666]

Re: Different timing behavior in RTL & Gate Level netlist simulation (using Cadence i

In your RTL simulation if A1 becomes 1 at 100ns, there is no way A2 can also become 1 at 100 ns. A2 should become 1 on the next rising edge of clock. This is because A2 is under clock.
If you are seeing A2 going high at 100 ns, there seems to be an issue in your RTL sim itself.