yuhiub90
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guys, I have a problem when simulating my design in Synopsys VCS. The simulation went wrong with all register contains X when I simulate my design in command line mode. But it run normally in GUI mode (i.e, invoke vcs compile with -R -gui options).
So what's the different between 2 mode simulation (any implicit options in GUI mode)?
Here's my current vcs options in command line:
Thanks,
Huy Bui
So what's the different between 2 mode simulation (any implicit options in GUI mode)?
Here's my current vcs options in command line:
Code:
vcs +v2k +evalorder -R -sverilog -MupdateThanks,
Huy Bui