One more thing I understand that LL transistors have lower leakage power dissipation than SP transistors.
In my design there will be some analog and digital blocks. I have decided to use the SP transistors for analog blocks in order to achieve the required performance parameters. And I want to use the LL transistors for the digital blocks. I also want to scale the VDD of the digital blocks to operate them in either in cutoff or subthreshold region.
Will the power dissipation for the digital blocks be reduced if I follow this method?