[SOLVED] Different MOS in UMC 90nm

[Debdut]

Hi,
I am using umc 90nm technology. There are 2 types of transistors in the library SP (Standard Process) and LL (Low Leakage).
Can I use both of them in the same design?

 

[erikl]

Yes. They have different threshold voltages (LL has higher |Vth|). Technology will take care of it (different bulk or gate doping).

 

[Debdut]

One more thing I understand that LL transistors have lower leakage power dissipation than SP transistors.
In my design there will be some analog and digital blocks. I have decided to use the SP transistors for analog blocks in order to achieve the required performance parameters. And I want to use the LL transistors for the digital blocks. I also want to scale the VDD of the digital blocks to operate them in either in cutoff or subthreshold region.
Will the power dissipation for the digital blocks be reduced if I follow this method?

 

[erikl]

... And I want to use the LL transistors for the digital blocks. I also want to scale the VDD of the digital blocks to operate them in either in cutoff or subthreshold region.
Will the power dissipation for the digital blocks be reduced if I follow this method?

Sure it will, but their max. operation speed as well. Make sure they still work as expected at your reduced op. voltage; optionally consider some voltage drop on chip.