[SOLVED] Different layers in vituoso

[techgig]

Hi all,

I'm new to Cadence Virtuoso. Please help me with the different layers used and why they are used in virtuoso.

In the below attached screenshot(it's for inverter, but not completed yet) I have got 2 doubts, namely

1. For both PMOS(top) & NMOS, why PIMP/NIMP is kept around poly?

2. For NMOS, why the PWdummy(p-well, I think so) layer is used?

I'm familiar with Synopsis custom designer, but new to virtuoso.

Thanks in advance.

 

[dick_freebird]

Poly must be implanted to get decently low resistance,
and to get the proper gate threshold (in concert with
the well doping on the other side of the gate oxide).
Siliciding can drive down R but undoped poly is prone
to poly-depletion issues affecting VT control and gate
linearity.

PWell is often really just a threshold-adjust implant,
although it may go deeper in some technologies. It
is a process control-point (starting material tends to
be "binned" very loosely, doping-wise, and you want
to start at a concentration lighter than anything else
you would want to do later, meaning VT of NMOS in
starting background material may be more like a
"native" (VT ~ 0) than a "digital" (VT ~ VDDspec/5)
transistor.

This really hasn't to do with Virtuoso or any other
specific CAD platform, the same was true when we
designed with pencil schematics, hand typed SPICE
netlists and Calma layout stations (CMOS being only
a curiosity in the days of rubylith, pretty much).

 

[techgig]

Thanks a lot dick_freebird!

That helped me in getting deep insight into it.