Difference in pre and post layout simulation

[vashistha]

I am working on the layout design of reference current circuit. The simulation result from schematic are 10 uA for both nmos & pmos but when i do the post layout simulation the output is 8.78 uA for nmos & 6.96 uA for pmos. Please suggest me how to optimize my layout so that pre & post layout simulation result will match.

Thanks

 

[kwagjj]

I'm not an expert but from what I know, you'll just have to adjust it with your own hands... The post layout simulation adds all the parasitic components analyzed from your layout to the original schematic. I guess in your case, the parasitic caps or resistances have affected your outcome.

one way is to look closer to your layout and try to find some layout designs that might increase unwanted capacitances or resistances.

another would be to adjust the schematic based on your understanding of the circuit to compensate for the parasitic effects caused by the layout.