If the essence of this Qn is "To synthesize same module on different FPGAs", then Max. Clock Frequency (operating) depends on Technology & Speed Grade of FPGA device being targetted.
And if the essence is "To synthesize same module with Constrained and Unconstrained Clocks", then Synthesis tool tries to achieve the best results of Max Op. Freq. for unconstrained clock, depending on the Optimization Goal. While in case of Constrained Clock, it tries to achieve the same with reference to the Constrained clock frequency. Please correct me if something didn't click..