Difference in frequency of clock

[eeeraghu]

Hello,

Why does the difference come in the frequency when the clock is unconstrained in different fpga's (altera, xilinx) when a module is synthesized? Even the architecure is different for different fpga's i believe the clock should be the same. is it right anway?

 

[Prasanna Kumar]

The clock is generated differently in different FPGA's with diffferent frequency, due to that there would be offcourse change in the frequency

regards

 

[Kulprashant]

hi,
no it should be different for different fpgas.

with regards,
kul.

 

[tkbits]

Are you talking about operating frequency or maximum operating frequency?

Operating frequency is not determined by the FPGA. It's determined by the clock signals that are supplied to the FPGA.

Maximum operating frequency is dependent on speed of logic, and on routing delays.

 

[Renjith]

Hello,

Why does the difference come in the frequency when the clock is unconstrained in different fpga's (@ltera, xilinx) when a module is synthesized?

As the architectures differ, so does the delay of the logical/routing elements.
so we cannot assume for the same performance for a particular design on these different targets. so even it ur clock is unconstrained, the synthesis tools will give different values.

 

[claint]

If you unconstrained the design, it is hard to estimate the frequency.

 

[Sparc]

If the essence of this Qn is "To synthesize same module on different FPGAs", then Max. Clock Frequency (operating) depends on Technology & Speed Grade of FPGA device being targetted.
And if the essence is "To synthesize same module with Constrained and Unconstrained Clocks", then Synthesis tool tries to achieve the best results of Max Op. Freq. for unconstrained clock, depending on the Optimization Goal. While in case of Constrained Clock, it tries to achieve the same with reference to the Constrained clock frequency. Please correct me if something didn't click..