Difference betwen analyze -f verilog and read_verilog in DC

[shahal]

read_verilog -netlist

How are these two commands different?

analyze -f verilog

read_verilog

 

[Adam.Yakuvitz]

read_verilog synopsys dc

I may be missing something in this question. As the command suggests, read_verilog reads in the rtl and gate level netlists. The Analyze command on the other hand builds the design and stores in an intermediat (primitive-level) format.

- read design would spit out parsing type errors
- analyze would show any linking problems as in mis-matched port names etc between the verilog files etc.

--
ay

 

[Kenwood Ma]

read_verilog netlist rtl

read_verilog include two steps, that is, analyze and elaborate, but do not link the design automatically.

 

[deh_fuhrer]

reading verilog files using analyze command

through analyze and elaborate command you would specify the directory where you want the design files to be stored but in case of read_file the design files would get automatically stored in present working directory...

 

[usaid]

dc read_verilog

Elaborate allows you to specify architecture, and allows you to override parameter values...