Somewhat. its similar to when a single register is used within a slice. the slice is counted as being used, but additional logic could be packed into the slice in a different build.
The tools might avoid packing 18k BRAMs into the same 36k BRAM in order to meet timing constraints. The BRAMs are fairly sparse, which makes routing difficult. thus an available BRAM might be chosen to be close to the logic it connects to. this results in 2 partially used BRAMs, as opposed to 1 fully used BRAM. Had only 1 BRAM been used, there would need to be more routing between the BRAM and some of the logic it connects to. The tools will determine this. As the design fills up, more and more BRAMs will start getting shared.
Also, fifo's are a bit special. The logic for fifos can use a 18k or 36k BRAM, but you don't get to use 296 18k fifo's. you get 148 fifos, which can be 18k or 36k. An 18k fifo can share a BRAM with an 18k BRAM though.
I would guess if you added the .xco file from coregen, XST would have known about the resource usage. From what I recall, ISE can use the .xco file to get information about a given core.