eshbonzie
Junior Member level 3
hey guys,
I am trying ti implement a BRAM of any size as a first step...after reading for a while I knew that this can be done from the Xilinx Core generator where I can specifiy exactly what type of memory I want with write and read widths. However I also found a language template inside the ISE itself where I can use ready made template for the memory implementation.
I am convinced more with the Core generator, however I tried both and synthesized. The synthesis report for the core generator generated memory didn't include any BRAM details
Device utilization summary:
---------------------------
Selected Device : 5vlx110tff1136-1
Slice Logic Utilization:
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 0
Number with an unused Flip Flop: 0 out of 0
Number with an unused LUT: 0 out of 0
Number of fully used LUT-FF pairs: 0 out of 0
Number of unique control sets: 0
IO Utilization:
Number of IOs: 168
Number of bonded IOBs: 0 out of 640 0%
Specific Feature Utilization:
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
while the synthesis report for the language template memory included BRAM information and it was mentioned
Device utilization summary:
---------------------------
Selected Device : 5vlx110tff1136-1
Slice Logic Utilization:
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 0
Number with an unused Flip Flop: 0 out of 0
Number with an unused LUT: 0 out of 0
Number of fully used LUT-FF pairs: 0 out of 0
Number of unique control sets: 0
IO Utilization:
Number of IOs: 112
Number of bonded IOBs: 112 out of 640 17%
Specific Feature Utilization:
Number of Block RAM/FIFO: 1 out of 148 0%
Number using Block RAM only: 1
Number of BUFG/BUFGCTRLs: 2 out of 32 6%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
Am I misunderstanding something? if both ways are valid to implement BRAMs, then what is the difference between them?
any help would be appreciated.
Eshbon
I am trying ti implement a BRAM of any size as a first step...after reading for a while I knew that this can be done from the Xilinx Core generator where I can specifiy exactly what type of memory I want with write and read widths. However I also found a language template inside the ISE itself where I can use ready made template for the memory implementation.
I am convinced more with the Core generator, however I tried both and synthesized. The synthesis report for the core generator generated memory didn't include any BRAM details
Device utilization summary:
---------------------------
Selected Device : 5vlx110tff1136-1
Slice Logic Utilization:
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 0
Number with an unused Flip Flop: 0 out of 0
Number with an unused LUT: 0 out of 0
Number of fully used LUT-FF pairs: 0 out of 0
Number of unique control sets: 0
IO Utilization:
Number of IOs: 168
Number of bonded IOBs: 0 out of 640 0%
Specific Feature Utilization:
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
while the synthesis report for the language template memory included BRAM information and it was mentioned
Device utilization summary:
---------------------------
Selected Device : 5vlx110tff1136-1
Slice Logic Utilization:
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 0
Number with an unused Flip Flop: 0 out of 0
Number with an unused LUT: 0 out of 0
Number of fully used LUT-FF pairs: 0 out of 0
Number of unique control sets: 0
IO Utilization:
Number of IOs: 112
Number of bonded IOBs: 112 out of 640 17%
Specific Feature Utilization:
Number of Block RAM/FIFO: 1 out of 148 0%
Number using Block RAM only: 1
Number of BUFG/BUFGCTRLs: 2 out of 32 6%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
Am I misunderstanding something? if both ways are valid to implement BRAMs, then what is the difference between them?
any help would be appreciated.
Eshbon