rahdirs
Advanced Member level 1
Hi all,
I'm trying to clk gate a few registers for saving power & couldn't understand the following. Below is a snippet of what I've tried
Method 1 : where i explicitly coarse & fine gater
Method 2 : where it's implicit and gating
Method 2 shows power saving but method 1 doesn't. Why do I see the difference ?
~rahdirs
- - - Updated - - -
I think I've figured it out. It wasn't showing savings probably because I was using the bit-wise and (&) instead of the logical and (&&) ? Will try with this change
I'm trying to clk gate a few registers for saving power & couldn't understand the following. Below is a snippet of what I've tried
Method 1 : where i explicitly coarse & fine gater
Code Verilog - [expand] 1 2 3 4 5 6 always @(posedge clk) begin for (i =0; i < 255; i = i+1) begin if (we[i >> 5] & coarse_en) mem[i][0] <= mem_d [i][0] end end
Method 2 : where it's implicit and gating
Code Verilog - [expand] 1 2 3 4 5 6 7 8 always @(posedge clk) begin if (coarse_en) begin for (i =0; i < 255; i = i+1) begin if (we[i >> 5]) mem[i][0] <= mem_d [i][0] end end end
Method 2 shows power saving but method 1 doesn't. Why do I see the difference ?
~rahdirs
- - - Updated - - -
Method 1 : where i explicitly coarse & fine gater
Code Verilog - [expand] 1 2 3 4 5 6 always @(posedge clk) begin for (i =0; i < 255; i = i+1) begin if (we[i >> 5] & coarse_en) mem[i][0] <= mem_d [i][0] end end
I think I've figured it out. It wasn't showing savings probably because I was using the bit-wise and (&) instead of the logical and (&&) ? Will try with this change