A Signal in VHDL is a wire. A signal will be synthesized into a wire or a flip-flop/latch depending on how you use it. Signals are global, they are visible to the entire module/ entity.
A variable is a temporary storage element. Variables are local, i.e, they are only visible inside the process where you declare them. Variables are mostly synthesized into latches or FFs. Variables can only be declared and used inside a PROCESS.
Refer VDHL synthesis primer by J.Bhasker for more info.