Difference between signals and variables

[sachin maheshwari]

hi .....
can anyone tell me wat is the difference between signals and variables in VHDL

 

[zolam]

look at this like in mathematics : f(x)
F is the function following some rule and x is the parameter values

 

[sachin maheshwari]

thanx for the answer but i want more relevant answer.

 

[vlsi_whiz]

A Signal in VHDL is a wire. A signal will be synthesized into a wire or a flip-flop/latch depending on how you use it. Signals are global, they are visible to the entire module/ entity.

A variable is a temporary storage element. Variables are local, i.e, they are only visible inside the process where you declare them. Variables are mostly synthesized into latches or FFs. Variables can only be declared and used inside a PROCESS.

Refer VDHL synthesis primer by J.Bhasker for more info.

 

[tosonal.jain]

hi .....
can anyone tell me wat is the difference between signals and variables in VHDL

hello friend
U see here is adifference b/w variable and signal precisely

VARIABLE Vs Signals:

Variables tak less memory , while signals need more information to allow for scheduling and signal attributes.

* Variables are assigned values immediately while signals tak some time to be assigned a value i.e signals are not updated Immediately

*Signals hav the history but variables dont hav.

*variables are for temporary storage and hav no hardware significance.

 

[vinodkumar]

Hi
as far as iam concerned:
signal is a wire in VHDL where as variable is a temporary storage element(no HW synthesized);

if we want the value to change in the same cycle declare variable otherwise signal(in the next clock).

 

[megastar007]

Moreover, variables can also be synthezied to FF if reading was done b4 writing(assign). It is advantageous to use variable instead of signal in same process.

 

[sanjay298]

in VHDL for the signals the driver is created which assign the values at the scheduled time
but for the variables no such drivers are created.

the values to the variable are assigned without any delta delay but for the signals the values are always assigned after the delta delay if no delay is specified in assignment statement.