There should be a follow-up spec to TIA/EIA PN-4584 respectively IEEE Std 1596, but I didn't see it yet. But you'll find a lot of documents mentioning the said operation parameters. I didn't go further into it, cause SubLVDS is beyond my field of interest yet.
The SLVS is what you are searching for. It was driven by Nokia for interchip, not interboard coms. It is double terminated, could be scaled simply by changing the supply voltage and have power consumption at the theoretical minimum if the source termination resistor are taken also into account. The common-mode rejection is lower than LVDS. Nearly all FPGA use vendor specific SLVS up to 9Gb/s.
JEDEC has recently completed work on another standard that has some of the same attributes of GLVDS. It is known as SLVS, which stands for "Scalable Low-Voltage Signaling for 400 mV" (JESD8-13) and was published in October 2001. This interface is terminated to ground, and has two options for drivers and receivers. Receivers can be either single-ended or differential, and drivers are either for point-to-point or multidrop applications. Data rates are in the 1-3 Gbps range but only over extremely short distances of less than 30 cm. This limits the interface to fast chip-to-chip connections only. Due to the 400 mV swing and ground reference, the power supply rail is only 0.8 V, thus the interface is compatible with low voltage cores found on sub-micron ASIC chips
Thank you for pointing to the standard. As I understood from my previous search, there are other, possibly vendor specific, Sub-LVDS level specifications beside SLVS-400.