difference between conv_integer and to_integer

[sougata_vlsi13]

Is there any difference between mem(conv_integer) and mem(to_integer)....while writing the code of spram i have to use those functions...are they one and the same thing.....please help...

 

[satty_008]

Type conversion is a regular operation that is performed while writing VHDL code, but it can sometimes be cumbersome to perform properly. An example of this is converting STD_LOGIC_VECTOR types to Integer types. You now have the following options to perform the same:

Function "conv_integer" defined in Synopsys Library : std_logic_arith, defined as:

function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
Function "To_integer" defined in IEEE library:numeric_std, defined as:
function TO_INTEGER (ARG: UNSIGNED) return INTEGER;
function TO_INTEGER (ARG: SIGNED) return INTEGER;
Of these, numeric_std is an improved package and has more ease of use. Following is example code describinghow to convert a STD_LOGIC_VECTOR to a signed Integer:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity conv_test is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : out integer);
end conv_test;
architecture Behavioral of conv_test is
begin
b <= to_integer(signed(a));
end Behavioral;
For unsigned integer, modify the snippet as:

b <= to_integer(unsigned(a));



They do they same operation !!

 

[TrickyDicky]

They are different. One is an IEEE standard (to_integer) and one is not standard VHDL (conv_integer).
Also, to_integer converts unsigned/signed type. Conv integer converts std_logic_vectors.

So, to do standard VHDL, you should use to_integer from numeric_std. You should never use std_logic_arith or std_logic_signed/unsigned