DCM vs counter clock
Whenever possible, I use counters instead of DCMs to generate new clock frequencies, because counters are plentiful, and they add almost zero jitter.
The DCM provides nice features such as phase alignment, phase adjustment, frequency doubling, and ratio frequency synthesis, but its DLL mechanism causes significant period jitter, sometimes several hundred picoseconds, and that hurts when clocking at several hundred MHz. For details, search for "jitter" in the DCM Switching Characteristics section of your FPGA data sheet. For some FPGAs, Xilinx provides a jitter calculator tool that predicts the jitter amount.
The Virtex-5 has PLLs that you can use to help remove jitter.