Difference between clock divided by DCM and by counter

[sameem_shabbir]

Hi all
Is there any difference between clock generated (divided infact) via DCM and divided via counter eg
reg [1:0] counter;

assign clk_div <= counter[1];

Will it divide the clock by 2 just as DCMs do.
Or are there any differences.

 

[echo47]

DCM vs counter clock

I think you are referring to a Xilinx FPGA.

If 'counter' is an ordinary synchronous counter, then yes you can use one of its bits to clock other logic. However, you should buffer the new clock signal with a BUFG so it routes through a low-skew clock distribution net instead of through general routing paths. A low skew clock net is usually essential for reliably clocking other synchronous logic.

That approach provides lower jitter than a DCM, but it doesn't provide phase alignment/adjustment features like a DCM.

 

[xtcx]

Re: DCM vs counter clock

That approach provides lower jitter than a DCM,.

From your saying,can I consider DCM gives more jitter?...Also I use to generate 2MHz,200KHz,50KHz,20Khz from a clk source of 80Khz. till to date, I never have used DCM for that purpose, though I never cared of getting synchronous output, I just prefered a clk divider in my code....Is anything wrong in this approach?.Is there anything useful that the dcm could provide in this regard?..Plz suggest

 

[echo47]

DCM vs counter clock

Whenever possible, I use counters instead of DCMs to generate new clock frequencies, because counters are plentiful, and they add almost zero jitter.

The DCM provides nice features such as phase alignment, phase adjustment, frequency doubling, and ratio frequency synthesis, but its DLL mechanism causes significant period jitter, sometimes several hundred picoseconds, and that hurts when clocking at several hundred MHz. For details, search for "jitter" in the DCM Switching Characteristics section of your FPGA data sheet. For some FPGAs, Xilinx provides a jitter calculator tool that predicts the jitter amount.

The Virtex-5 has PLLs that you can use to help remove jitter.

 

[xtcx]

Re: DCM vs counter clock

Thanks you Echo47. I believe I'm on the right path and could you clear me this?...If I'm supposed to generate 2KHz,20KHz,2MHz clk(only eg) from a system clock of say 80MHz, which method(DCM or counter) provides synchronous clk output(jitter not bothered)for all clk dividers?...(Hope u understand what I mean)

 

[echo47]

DCM vs counter clock

To keep the timing clean and simple and synchronous everywhere, you could clock everything at 80 MHz, and then build some simple counters that generate strobe pulses at 2 kHz, 20 kHz and 2 MHz, and then use those strobe pulses as clock enables for the low-speed sections of your project. That's how I build most of my projects. However it does consume a little more power, and a little more routing resources.

 

[xtcx]

Re: DCM vs counter clock

Ok Thanks my friend!...

 

[pramodm]

DCM vs counter clock

If we use both source clock(before divide) and derived clock(after dividing) in our design, if is there any data paths between these two clock domains the clock skew between source clock and destination clocks we need to consider when we use counter clock but if we use DCM the de-skew capability of DCM automatically adjust the skew without entering any attribute in our design

 

[echo47]

DCM vs counter clock

Remember that Xilinx DCM's can't generate low frequencies such as 2 kHz and 20 kHz.