Did I correctly implement this SR-Latch and D-Latch?

[delta136]

Hey everyone! Would greatly appreciate it if someone could look over my code and tell me if I implemented this correctly.

1-bit SR-Latch: (Teacher provided the diagram and truth table)


Code here: (c is for the clock)

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Code Verilog - [expand]
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module sr_latch(output q,
                    output q_not,
                    input s,
                    input c,
                    input r);
     
      wire n1_out;
      wire n2_out;
      wire n3_out;
      wire n4_out;
     
      nand n1(n1_out, s, c);
      nand n2(n2_out, c, r);
      nand n3(n3_out, n1_out, n4_out);
      nand n4(n4_out, n3_out, n2_out);
     
      assign q = n3_out;
      assign q_not = n4_out;
    endmodule

---

1-bit D-Latch:


Code here:

---

Code Verilog - [expand]
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module d_latch(output q,
                   output q_not,
                   input d,
                   input c);
     
      wire inv_out;
      wire n1_out;
      wire n2_out;
      wire n3_out;
      wire n4_out;
     
      not(inv_out, d);
      nand(n1_out, d, c);
      nand(n2_out, c, inv_out);
      nand(n3_out, n1_out, n4_out);
      nand(n4_out, n3_out, n2_out);
     
      assign q = n3_out;
      assign q_not = n4_out;
    endmodule

---

The reason I ask for someone to look over it is because I'm not sure if my code reproduces the two truth tables.

And lastly, the ultimate goal is to use the SR-latch and D-latch to make a Flip Flop (That's a D-Flip Flop, right?)

Can someone explain to me what the 'P' is in the flip flop? Why does the truth table contain only Q and not Q' like the above pictures, yet the output of the flip flop has Q and Q'?

Thank you very much for your time and help!

 

[ads-ee]

Both the code for the sr and d latches matches their respective circuit diagrams. To determine if the truth table is correct: apply each input to the circuit an verify the next output is the same as the table.

P is a preset and R would be the reset. The missing Q' probably was an oversight or the truth table was for a d-ff without a Q' output.

 

[FvM]

To be correct for a positive edge triggered DFF according to the symbol, the third truth table should have a rising edge symbol (e.g. up-arrow) in the C column instead of 1.

 

[delta136]

Both the code for the sr and d latches matches their respective circuit diagrams. To determine if the truth table is correct: apply each input to the circuit an verify the next output is the same as the table.

P is a preset and R would be the reset. The missing Q' probably was an oversight or the truth table was for a d-ff without a Q' output.

Sorry for being clueless, but how could I verify the next input? I only know how to verify Q(t) and not Q(t+1)

Here's the test bench I wrote using inputs from the truth table:

module sr_latch_test;
  
  wire q;
  wire q_not;
  reg s;
  reg c;
  reg r;
  
  sr_latch test1(.q(q), .q_not(q_not), .s(s), .c(c), .r(r));
  
  initial
    begin
      $monitor($time, " c = %b, s = %b, r = %b, q = %b, q_not = %b", c, s, r, q, q_not);
      
#5	  c = 1'b1; s = 1'b1; r = 1'b0;      
#5	  c = 1'b1; s = 1'b0; r = 1'b1;
    end
endmodule

Output:
#5 c = 1, s = 1, r = 0, q = 1, q_not = 0
#10 c = 1, s = 0, r = 1, q = 0, q_not = 1

module d_latch_test;
  
  wire q;
  wire q_not;
  reg d;
  reg c;
  
  d_latch test1(.q(q), .q_not(q_not), .d(d), .c(c));
  
  initial
    begin
      $monitor($time, " c = %b, d = %b, q = %b, q_not = %b", c, d, q, q_not);
      
#5	  c = 1'b1; d = 1'b1;    
#5	  c = 1'b1; d = 1'b0; 
    end
endmodule

Output:
#5 c = 1, d = 1, q = 1, q_not = 0
#10 c = 1, d = 0, q = 0, q_not = 1

 

[ads-ee]

Given the above diagram and your original truth table.

c =0, s=x, r=x, Qt=0:
If C is 0 then both ng1 and ng2 are 1.
if the original output of Qt was 0 then the next output of Qt (Qt+1) will be 0

looking at the third row:
c=1, s=1, r=0, Qt=x(0/1):
C is 1 so both gates 1 & 2 are enabled and the value on S and R are inverted.
therefore ng1=0 and ng2=1, with ng1 forcing gate 3's output to 1 (new Qt+1) as it is forced we don't care what Qt was hence the X input
now that Qt+1 is 1 the feedback through gate 4 along with ng2 means Q't+1 will be 0.

 

[delta136]

Ok, last question, I promise!

What's wrong with my Flip Flop? My output for Q and Q' are both x. Any ideas why?

module flipflop(output q,
                output q_not,
                input p,
                input d,
                input c,
                input r);
  
  wire [1:0] inv_out;
  wire [7:0] nand_out;
  
  not(inv_out[0], d);
  not(inv_out[1], c);
  
  nand(nand_out[0], d, c);
  nand(nand_out[1], c, inv_out[0]);
  
  nand(nand_out[2], p, nand_out[0], nand_out[3]);
  nand(nand_out[3], nand_out[2], nand_out[1], r);
  
  nand(nand_out[4], nand_out[2], inv_out[1]);
  nand(nand_out[5], inv_out[1], nand_out[3]);
  
  nand(nand_out[6], p, nand_out[4], nand_out[7]);
  nand(nand_out[7], nand_out[6], nand_out[5], r);
  
  assign q = nand_out[6];
  assign q_not = nand_out[7];
endmodule

Output:
5 c = 1, d = 0, p = 1, r = 1, q = x, q_not = x
10 c = 1, d = 1, p = 1, r = 1, q = x, q_not = x

Am I using the 3-input NAND primitive incorrectly?

 

[sharath666]

Why are you using a 3 input NAND gate? Shouldn't u be using a 2 input one instead. Is the third input X?

 

[delta136]

The diagram drawn by my teacher and attached in the previous post calls for a NAND gate with 3 inputs. The third input is for the "Preset" and "Reset" at NAND gates 3, 4, 7, and 8 in the diagram (from left to right)

I tried to convert the 3 input NAND gate into two 2 input NAND gates but somehow got an infinite loop because when I run the simulation, it never runs until completion. It eventually times out

Did I not do the conversion correctly?

This causes a time out when ran

module flipflop(output q,
                output q_not,
                input p,
                input d,
                input c,
                input r);
  
  wire [1:0] inv_out;
  wire [11:0] nand_out;
  
  not(inv_out[0], d);
  not(inv_out[1], c);
  
  nand(nand_out[0], d, c);
  nand(nand_out[1], c, inv_out[0]);
  
  nand(nand_out[2], p, nand_gate[0]);
  nand(nand_out[3], nand_out[2], nand_out[5]);//
  
  nand(nand_out[4], nand_out[3], nand_out[1]);
  nand(nand_out[5], nand_out[4], r);
  
  nand(nand_out[6], nand_out[3], inv_out[1]);
  nand(nand_out[7], inv_out[1], nand_out[5]);
 
  nand(nand_out[8], p, nand_out[6]);
  nand(nand_out[9], nand_out[8], nand_out[11]);
  
  nand(nand_out[10], nand_out[9], nand_out[7]);
  nand(nand_out[11], nand_out[10], r);
  
  
  assign q = nand_out[9];
  assign q_not = nand_out[11];

 

[sharath666]

Ok. You have used the same instance for both the 2 input as well as 3 input nand gates. Will that work?

 

[ads-ee]

Try setting R or P to 0 first.

- - - Updated - - -

actually I just tried simulating the code from post #6 and it works without issue.



Maybe you aren't toggling the clock (c)?

Post the testbench or the actual ?Modelsim? commands you use to test the design.

- - - Updated - - -

Ok. You have used the same instance for both the 2 input as well as 3 input nand gates. Will that work?

the built in AND/NAND/OR/etc... primitives in Verilog can accept any number of inputs.


FYI, you should include instance names for each instantiated primitive or module.

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// instead of this:
  nand(nand_out[0], d, c);
  nand(nand_out[1], c, inv_out[0]);
 
// do this:
  nand n1 (nand_out[0], d, c);           // nand instance 1
  nand n2 (nand_out[1], c, inv_out[0]);  // nand instance 2

---

This way you'll know what the name of each instance is as opposed to just letting the tools make up stuff.

- - - Updated - - -

The code in post #8 has some kind of oscillation in the feedback path, I'm not going to look into it further, as the code in post # 6 works correctly.