Output waveform problem for SR latch in Verilog

[shockingshockley]

Hello. I am implementing this SR latch circuit below using Verilog:

This is the expected logical truth table for this SR latch:

This is the Verilog code I wrote:

The corresponding technology map is this after I compile the Verilog code. It is not the same as the NAND SR latches.

After compiling, I run the functionality check to observe the input and output waveforms:

However, the output Q is always logic 1 throughout the period. It should have an undefined outputs of 0 and 1. Could you please advise me what is something wrong in my Verilog implementation and behavioral simulation? Thanks in advance.

 

[KlausST]

Hi,

Try this:
Take a pencil and a paper ... and draw strictly what your code says.
Then compare it with the given schematic.

In case it's still unclear, please show your drawing.

Klaus

 

[dpaul]

@shockingshockley
If you want to implement exactly the SR latch circuit as in pic1, you need to use some SPICE simulations tool such as Tanner EDA.
In FPGA you have only LookupTables, Flipflops and Multiplexers as the most basic implementation elements. So when you synthesize a Verilog code, the structure will be different than as in the pic1. But the functionality will be the same.

 

[FvM]

As dpaul clarified, the Verilog description and the gate level circuit are functional equivalent.

The main problem of post #1 is however the confusion about "undefined". Seeing level '1' in a specific test case doesn't contradict the general specification as undefined. Your testbench must include all input signal combinations and respective transistions to see the different output states for input "11".

 

[BradtheRad]

The SR flip-flop is a basic memory cell. There are certain situations which cause a change of state when you change an input.
And certain situations where no change of state occurs when you change an input.

Sometimes the Q output changes yet Q-bar does not. Or vice-versa.