[DFT] Flash memory testing method

[maulin sheth]

Hello All,
Can anyone please tell me that which DFT methodology is used to test Flash Memory?
Which EDA tools are available for same?

Thanks in advance.

With Regards,
Maulin Sheth

 

[rca]

well, the flash tests are define by the Flash providers.
Some BIST vendor could generate your own BIST algorithms, usually the FLASH is associated to a dsp or processor, and the BIST is coded in software on this core.
And we usually add a test mode to have a direct connection to the Flash pins and in case any issue, test the FLASH from the pins.

 

[maulin sheth]

Thanks rca.
So, flash testing architecture is provided by flash provider only.
But flash provide use which DFT methodology for testing flash memory?
They are taking any EDA tool support? If yes, than which EDA tool used?
if Flash is associated with dsp, thn is it analog design?

As you said "And we usually add a test mode to have a direct connection to the Flash pins and in case any issue, test the FLASH from the pins."
How can we have a direct connection to the flash pins? Do we need to put BIST to apply data and address for direct connection to flash pins?

Thank you very much.

Thanks & Regards,
Maulin Sheth

 

[rca]

Flash provider indicates the algorithm or the test to be done, no architecture and no DFT methodology are indicated!
In Tessent Bist tool from Mentor, the BIST algorithm could be modify/create by the user to fit his own desire.
The direct pin access, is a test mode, we code the RTL to have this direct access, or to mapped all the pins to an address, and so the processor (or dsp) could "stimulate" the Flash.