Mar 22, 2005 #1 A akrlot Member level 3 Joined Jan 14, 2005 Messages 55 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 450 hi; my synthesis script contains these line read -format VHDL fsm.vhd current_design feu_ctl --feu_ctl is the name of entity in fsm.vhd i get this message: cant find the design feu_ctl how to resolve this problem.thx
hi; my synthesis script contains these line read -format VHDL fsm.vhd current_design feu_ctl --feu_ctl is the name of entity in fsm.vhd i get this message: cant find the design feu_ctl how to resolve this problem.thx
Mar 23, 2005 #2 M mediatek Member level 1 Joined Sep 5, 2003 Messages 41 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 334 Re: dft compiler problem this message means you set the wrong top name. You need to check your top design name(try to find entity aaa (vhdl) or module aaa(verilog)) . you can use ==>remove_design -all to cancel all design first then set current design again. ===> current_design aaa
Re: dft compiler problem this message means you set the wrong top name. You need to check your top design name(try to find entity aaa (vhdl) or module aaa(verilog)) . you can use ==>remove_design -all to cancel all design first then set current design again. ===> current_design aaa
Mar 25, 2005 #3 J JesseKing Advanced Member level 4 Joined Nov 12, 2004 Messages 100 Helped 3 Reputation 6 Reaction score 1 Trophy points 1,298 Activity points 838 dft compiler problem btw, this is design compiler