DFFR question Related to sizing

[_SquiD_]

DFFR Related

Can anyone help with the understanding of the gate sizing from this DFFR (D flip-flop with Reset) (see the attachment). I don't really know if I done the sizing right.
The thing is that DFFR circuit doesn't work ... it stays blocked in 0 (concluzion after a .tran simulation).

Can anybody take a look ? Thx in advance.

_Squ!D_

 

[Blackuni]

Re: DFFR Related

Hi,


have u set initial conditions for transient simulation? if not please set it to proper values.

before doing that Also check your operating point report to make sure the node voltages make sense.

once this is done , then you can focus on sizing based on the requirement/performance.


SPICE do have problem in simulating digital circuits that tooo closed loop ckts.


Thanks,