Determining the amount of clock loads

[TonyLS]

How can I determine the amount of flops on a particular clock domain within dc_compiler or prime-time? Also I want this report to consider the output load of clock gate cells for each clock domain. Although if there is a DC command before compile that analyzes the RTL for clock loading then clock gating wouldn't be an issue.

The design does not have a synthesized clock tree yet. RTL analysis is fine.

I can obtain the answer out of the DFT process, but I'd rather get it up front from dc_compiler.

Thanks