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Desing of starved current VCO - transistor's sizes

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Florian90

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Hello everyone,
I am trying to design a starved current ring oscillator based with CMOS 0.35u having to emit 100MHz. I dont have much power limitation (meaning i can go up to several hundreds of uA) but I am using this oscillator as a part of a temperature and process independent design.
I have looked a lot of paper and publications about this subject and none of them explain their choice of W/L of both the inverters and currents mirrors. Also i have seen different types: mirror's W/L > inverters, inverters W/L > mirrors or even equal. I have the impression that everyone does it on an empiric way just by testing and do not actually explain why.
So I am asking, is there a rule about this design? What kind of values i need? it should probablly be related with 2 factors:
1- Parasit Capacity of the inverter
2- Current limitations

Thanks in advance
 

Debasish_Halder

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You should go for gm/Id methology to determine the optimum W/L ratio of each transistor. It also give a vivid picture to the region of transistors. So go for it....
Hello everyone,
I am trying to design a starved current ring oscillator based with CMOS 0.35u having to emit 100MHz. I dont have much power limitation (meaning i can go up to several hundreds of uA) but I am using this oscillator as a part of a temperature and process independent design.
I have looked a lot of paper and publications about this subject and none of them explain their choice of W/L of both the inverters and currents mirrors. Also i have seen different types: mirror's W/L > inverters, inverters W/L > mirrors or even equal. I have the impression that everyone does it on an empiric way just by testing and do not actually explain why.
So I am asking, is there a rule about this design? What kind of values i need? it should probablly be related with 2 factors:
1- Parasit Capacity of the inverter
2- Current limitations

Thanks in advance
 

Florian90

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You should go for gm/Id methology to determine the optimum W/L ratio of each transistor. It also give a vivid picture to the region of transistors. So go for it....
Hello,
Thanks for answering. Could you explain me a bit more this gm/ID methology please? I am new to CMOS techonology. Or if not could u point me out at some documets which explain/have an example of this methology?
Thanks
 

Debasish_Halder

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Hello,
Thanks for answering. Could you explain me a bit more this gm/ID methology please? I am new to CMOS techonology. Or if not could u point me out at some documets which explain/have an example of this methology?
Thanks
use these papers

- - - Updated - - -

use these papers
you can also use a book named tradeoffs and optimization in analog cmos design by David Binkley
 

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Florian90

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Thanks, I will check them out. But on a first look they all work with OTA amplifiers, I am using inverters for my VCO, will the gm/I method still apply the same for the inverters?
 

Debasish_Halder

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you just take the concepts to optimize your circuit transistor....
Thanks, I will check them out. But on a first look they all work with OTA amplifiers, I am using inverters for my VCO, will the gm/I method still apply the same for the inverters?
- - - Updated - - -

like if u design a circuit in saturation region than the on transistors should be in saturation and off ones should be in cut off.and this gm/id plot give a vivid picture of a transistor region and related w/l ratio...
you just take the concepts to optimize your circuit transistor....
 

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