Designing SSRAM based queue with different clock rate at I/O

[Zerox100]

Fifo

Dear my friends,
I want to design a ssram based queue with diffrent clock rate at input and output. I test some idea but these are not good. I need some stuff.
Thanks,

 

[lollobrigido]

I used, for similar applications a circular queue, so if you need you can overwrite the unreaded old data.

Lollo

 

[mami_hacky]

Would you please describe the idea more? Does your fifo use an on chip memory, or your memory is a sepatate memory component out of the chip? Then you have to find good dual port memories.
any how the main idea for an asynchronous fifo is simple. you can find the needed material by a simple search. there is always a read controller, a write controller, a dual port memory, and two clock synchronization circuits. The design is simple and easy to understand.

 

[Zerox100]

Would you please describe the idea more? Does your fifo use an on chip memory, or your memory is a sepatate memory component out of the chip? Then you have to find good dual port memories.
any how the main idea for an asynchronous fifo is simple. you can find the needed material by a simple search. there is always a read controller, a write controller, a dual port memory, and two clock synchronization circuits. The design is simple and easy to understand.

I want to build it on FPGA and i want to use dual port bram as on chip memory (fifo width = 8bit, length = 64byte). I need some status signal like empty and full. I prefer synchronous fifo with dual clock rate at ports.

 

[dainis]

Look at:
https://www.opencores.org/projects/generic_fifos/