Designing SDR Platform

[kangalooj]

I need to generate a signal have 16-bits samples (I and Q each 16bits) with 8 MSps sample rate, to use with my SDR (Software Defined Radio).

I want to generate signals on the fly, so I can't store signal on disk and I must have near real-time communication with the hardware (a buffer of 100 to 200 milliseconds is acceptable).

Bit rate this needs is about 16 (samples resolution) * 2 (I+Q) * 8e6 (sample rate) = 256 Mbps = 32 MBps ! So it seams USB is not a safe and reliable solution for communication with HW.

I think the best solution here is a PCI-Express card (x1 lane is best choice and enough) that have a simple and cheap FPGA like Xilinx spartan 6 or Altera Cyclone IV GX (both have IP-Core for x1 lane PCI-e Gen 2) interfacing with a high-speed DAC (Texas Instrument DAC34xx or DAC5687) and also have a RAM for buffering samples.

How can I design this board ? is there any example to help me?

 

[Zerox100]

if you want to generate a random code it is too easy. Create a random generator in FPGA and feed outputs to your SDR.
But if you want to generate a pre-defined test vetor and feed it to SDR it is a bit complex.

 

[kangalooj]

My SDR must feed the signal generator! I want to generate samples in my SDR and transfer it to DAC via PCI-Express.

 

[Zerox100]

Could you please describe what you want with a diagram or a graphical representation for me?

 

[yourcheers]

My SDR must feed the signal generator! I want to generate samples in my SDR and transfer it to DAC via PCI-Express.

U need not to use pcie here, you can directly interface DAC to the FPGA.
Already there are some xilinx appnotes present on how to interface DAC to FPGA. Search in xilinx site..

 

[kangalooj]

I have designed SDR (Software Defined Radio) that works with PC (and only PC with Windows because my SDR written in C#!). My SDR produce signal samples (16bit I/Q with 8MSPS rate) that I need generate them in real world ! So I need an interface between PC and second HW that generates signal to the real world and here comes PCI-Express as this interface.

So samples are in PC RAM => I transfer them to signal generator via PCI-e => I may use FPGA's IP Core to implement PCI-e in Signal generator => FPGA gets samples from PCI-e bus and gives them to DAC!

Now! how can I design this Signal generator?!

 

[mrflibble]

You haven't really motivated the use of PCIe for something with such a pifflingly low bitrate. What is wrong with say usb? Or gbit ethernet? Some people might argue that usb/ethernet is a whole lot easier than using PCIe. Especially since you seem to imply (with the 100-200 ms buffer size) that latency is not too much of an issue.

Unless of course you are looking for 1) an excuse for PCIe and 2) a nice steep learning curve, then gogogo!