Designing PLL with FPGA for a final year project !

[arbalez]

designing pll with fpga

i want your opinion on designing an all-digital phase locked loop. is it quite easy for a final year project? or is it worth to be a final year project? my lecturer said it is easy to design such pll with fpga. and the analog one is much tougher. so should i proceed or design an analog one? please write your suggestion. tq.

 

[arunragavan]

Re: designing pll with fpga

well design of a ADPLL is kinda simple.. well wot u have to understand are the basic buildin blocks in an ADPLL

The first is the PFD followed by a low pass filter and finally a DOC - digital control oscilloscope.

Try to simulate these blocks u wud obtain the output for ur ADPLL.. both phase and frequency has to lock.

I have some materials on ADPLLs..i can upload them if required.

with regards,

 

[arbalez]

Re: designing pll with fpga

i think i need it. can you please upload the files?
does writing vhdl code for adpll a hectic one?
thanks.

 

[arunragavan]

Re: designing pll with fpga

Well here is a document which contains information on ADPLLs


Digital Phase Locked Loops



Mike DeLong

13 May 2004

Topic
The topic for this technical paper will be FPGA implementation of digital phased locked loops.

Hope this helps you

with regards,

 

[tmsupon]

Re: designing pll with fpga

Well here is a document which contains information on ADPLLs


Digital Phase Locked Loops



Mike DeLong

13 May 2004

Topic
The topic for this technical paper will be FPGA implementation of digital phased locked loops.

Hope this helps you

with regards,

Hey, can you help me with the design of a ADPLL? I do not have any special requirement, I only have to implement any kind of PLL in a FPGA board. Even if you can give VHDL/Verilog code for any PLL that I can implement in FPGA, that will do. I tried using the built in PLL, but the problem is I have to access the feedback path and I don't know if or how can I access the feedback path of the built in PLL.

 

[mrflibble]

Re: designing pll with fpga

Hey, can you help me with the design of a ADPLL? I do not have any special requirement, I only have to implement any kind of PLL in a FPGA board. Even if you can give VHDL/Verilog code for any PLL that I can implement in FPGA, that will do. I tried using the built in PLL, but the problem is I have to access the feedback path and I don't know if or how can I access the feedback path of the built in PLL.

That last post is 6+ years old, so ... ?

Regardless, you might want to take a look on opencores.org. I recall seeing a few ADPLL's on there.