arbalez
Member level 5
designing pll with fpga
i want your opinion on designing an all-digital phase locked loop. is it quite easy for a final year project? or is it worth to be a final year project? my lecturer said it is easy to design such pll with fpga. and the analog one is much tougher. so should i proceed or design an analog one? please write your suggestion. tq.
i want your opinion on designing an all-digital phase locked loop. is it quite easy for a final year project? or is it worth to be a final year project? my lecturer said it is easy to design such pll with fpga. and the analog one is much tougher. so should i proceed or design an analog one? please write your suggestion. tq.