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designing non-overlap clock signal using counter

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shockingshockley

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Hello. I am designing non overlapping circuit using counter. I would like Q1 and Q7 be non-overlap. Maybe increasing delay at Q7? Could you please provide me solution? WIll adding buffer helps? Or any suitable solution? THanks in advance.
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barry

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By design, Q1 is simply Q7 delayed by 2 clocks. You could add two more registers to delay Q7 by 2 clocks such that Q7 would look like the inverse of Q1. Or, you could just invert Q1. Without more information about exactly what YOU mean by 'non-overlapping' and what you're trying to do, it's hard to answer.

But, you can't have two 50% duty cycle clocks like you've got and have them be 'non-overlapping' in the normal sense; their edges will overlap. If you do a web search, you'll find LOTS of non-overlapping clock circuits.
 
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