[SOLVED] designing footprints for QFN packages

A brief summary…
1oz copper is not very good at spreading heat, I have to tweak this area to achieve the more critical requirements in doing so I added some thermal vias as there were none… I could only resume this was because of all the components blocking the way, as the design needed to get the design done I did not want to be back and forth asking questions and as I have done hundreds of designs with these devices on since early 2000 I follow BEST PRACTICE for both reliability and thermal considerations. My go to guide is the IPC specification IPC-7093, but I also have an extensive library covering these components and more specifically PCB thermal design I also refer to a whole bibliotheca of relevant material, a little sample below:
IPC-7093
**broken link removed**

https://www.smtnet.com/library/file...-design-optimal-qfn-yield_reliability-ipc.pdf

https://www.ti.com/lit/an/snva183b/snva183b.pdf

https://www.ti.com/lit/an/snva419c/snva419c.pdf

https://www.cirrus.com/en/pubs/appNote/AN315REV1.pdf

https://www.ti.com/lit/an/snva183b/snva183b.pdf

https://www.vision-systems.com/arti...meras-tackle-pcb-inspection-applications.html

So I can quickly remove the vias, but my recommendation would be to follow industry standard practice with these devices and use thermal vias.

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