designing divide by 3/2 counter

[ASIC_intl]

clock_dividers_made_easy

How to design a divide by 3/2 counter which is synthesizable?

 

[natg9]

Re: designing divide by counter

Hi pal


i have a doc regarding the same
but due to some reason i m getting this error msg from EDABOARD

Sorry but this file has already been posted! Better copy and paste following link into your post, where the same file is located:




so give me ur email id i ll post it to u


regards
natg

 

[AdvaRes]

Hi,

Yeah use the document Clock_Dividers_Made_Easy.pdf, it is very usefull. You can make easily 1/2,3/2 and 1/5 divider with 50% duty cycle

 

[ASIC_intl]

Can u make a divide by 3/2 counter with using of two FSMs among them one operates in positive edge and the other at negative edge.

The clock_divider_made_easy.pdf approach is different.

 

[speedforu]

lep is the pulse you generate whenever you FSM counter counting clock edges becomes 0. lep_d1 is the output of the register with input lep clocked on negative edge. The output is a simple OR of these 2 signals.

 

[ASIC_intl]

we want a divide by 3/ 2 counter not a divide by 3 counter whose timing diagram has been drawn.

 

[dcreddy1980]

Hi ASIC_intl, Can you give me a reason why do u want to go for FSM approach for the divide by 3/2 clock generation?

 

[ASIC_intl]

There is no reason particularly. It can be done in that way also. The way suggested by the document of STMicroelectronics is a traditional approach.

Can u solve in the way I stated!

 

[Peter Chang]

I think it needs a PLL.


Peter