For a better understanding of your design, you should tell the full specification of your CIC decimator. The width of individual integrator stages is commanded by the output width, CIC order and decimation factor. It doesn't necessarily imply that all bits are significant. Some bits may be also omitted by applying Hogenauer's pruning theory.
I don't think, that insignificant CIC bits are random. They'll rather show patterns depending on the input sequence. But for a randomly varied input, they can be expected to be randomized as well.
Delta sigma modulation gains resolution by averaging many coarse samples. It's similar to averaging a noisy signal to increase the signal to noise ratio. The more samples you average, the better the signal to noise and thus the better the resolution.
You didn't tell the number of output bits.
No, that's not correct. Actually the first integrator needs the maximum bit width, the succeeding integrators and comb stages can possibly have a reduced width according to pruning calculations. I suggest to review Hogenauers original paper or some other CIC literature.For a 1024 OSR, output freq is 500 Hz, and each integrator needs bit increment of 10 bits. So input bits is 1, after first integrator it goes to 11, second one gives 21 bit output.
-- Stage 1 INTEGRATOR. Bit width : 21
-- Stage 2 INTEGRATOR. Bit width : 21
-- Stage 1 COMB. Bit width : 18
-- Stage 2 COMB. Bit width : 17
No, that's not correct. Actually the first integrator needs the maximum bit width, the succeeding integrators and comb stages can possibly have a reduced width according to pruning calculations. I suggest to review Hogenauers original paper or some other CIC literature.
I get e.g. these parameters for a 16 Bit output second order CIC. The additional output bit is provided for rounding purposes.
Code:-- Stage 1 INTEGRATOR. Bit width : 21 -- Stage 2 INTEGRATOR. Bit width : 21 -- Stage 1 COMB. Bit width : 18 -- Stage 2 COMB. Bit width : 17
P.S.: An edaboard member reminded me to this previous thread https://www.edaboard.com/threads/127067/
Yes, there's "some mathematics involved" and it's not very easy. It's exactly derived in Hogenauer's original paper and briefly described in U. Meyer-Baese DSP with FPGA. There'a simple formula for the bitwidth of the first integrator and a more complex calculation how to reduce it towards the output.Could you tell me how you reduced the bits from the second stage to the third and fourth ones? IS there some mathematics involved?
Not only is Bmax the MSB at the filter output, but it is also the MSB of all stages of the filter. This can be shown by applying modulo arithmetic to the filter output function. For two's complement arithmetic, the modulo operation can be implemented by simply eliminating bit positions above Bmax.
Since the modulo operation is used at the filter output, the same modulo operation can be applied independently to each integrator and comb stage. This implies that Bmax is an upper bound for each filter stage.
It is now shown that Bmax is also a lower bound. Since the first N stages of the filter are integrators with unity feedback, it is apparent that the variance of the integrators outputs grow without bound for uncorrelated input data. As seen at the output register, Bmax is the MSB for each integrator since this as a significant bit and is the highest order bit that can propagate into the output register. Since a propagation path must be provided through the comb section for this MSB, it can be be concluded the Bmax must be the MSB not only for the integrators, but also for the combs that follow.
For in=0: comb2=0x0000 0000; (correct to expectations)
For in=1: comb2=0x0000 1000; (expected 0xFFFF FFFF instead)
while(1)
{
for (n1=0;n1<64;n1++)
{
//if (in==1)
//{in=0;}
//else
//{in=1;}
//First integrator
integrator1=integrator1+in; // y(n)=x(n)+y(n-1)
integrator2=integrator2+integrator1; // z(n)=y(n)+z(n-1)
} // end for
// Start low speed operations here.
comb1=integrator2-last_integrator2; // First differentiation
// v(n)=z(n)+z(n-1)'+1
// First differentiation over
comb2=comb1-last_comb1; // w(n)=v(n)+v(n-1)'+1
// Second differentiation over
last_integrator2=integrator2;
last_comb1=comb1;
}
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