Designing a processor that is using several blocks

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masoud.malekzadeh

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HI , I 'm designing a processor that is using several Blocks , for example the output of Block A is input for Block B and so on ,,,,
and Block A needs 10 Clocks And B needs 6 , If i call these as files or Procedure The block B waits until the Block A finish ?

Thanks .
 

Re: Using file procedure


You could call each block as a procedure (not as a 'file'...a file has no real meaning in a design language, it is simply a holder for the actual design elements such as an entity, process, procedure, declarations, etc.). However, since each block has some state to it (since you said that block A takes 10 clocks, block B takes 6), then it would likely be a mistake to try designing the blocks as a procedure, they should be separate standalone design elements. Then there will be another entity that instantiates the two blocks and connects the signals together appropriately.

Entities (in VHDL) and modules (in Verilog) are the natural design hierarchy enclosure, use it, don't fight it and you'll be ahead of the game.

Kevin Jennings
 

Re: Using file procedure


You mean i define each block as a component then use port map to connect to each other ?
In this case The block B waits until the Block A to finish ?
 

Re: Using file procedure

you have not been very clear in your description. Can you please try and elaborate more.
 

Re: Using file procedure

TrickyDicky said:
you have not been very clear in your description. Can you please try and elaborate more.
Click to expand...

I want to calculate the covariance of some data , first i should calculate the mean of data then remove it at the end calculate the covariance , and each one needs some clock cycles e.g 8 clocks ,( my hole arithmetic operations need clock cycles to operate ) .

now my question is what should i do in order to the covariance block should operate when the data is valid i mean after removing the mean ?
 

Re: Using file procedure

are we talking about testbenching or the real design?
 

Re: Using file procedure

They will only work when you create the entities (VHDL) or Modules (Verilog) for them. Just having the components doesnt really do alot. if you have the source, you never need to declare components. Component declarations should only be used when you need to black box something, or the source code is in another language.
 

Re: Using file procedure



yes i mean i create an entity for each of them then portmap them will it work ?
 

Re: Using file procedure

The port map has nothing to do with the operation. You can separate out every single register if you real wanted. The important bit is the functionality. The port map just shows the connection between the entities.
 

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