J90
Junior Member level 1
I'm trying to implement a DDR2 controller on a Spartan3 FPGA.
The memory is a single 512Mb chip by Micron (32M x 16, that is the data bus is 16 bits wide), and the following is its datasheet: https://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf
Writing the RAM is quite straightforward, but reading it is giving me nightmares.
The DDR2 uses a source synchronous interface, that is the data on the parallel data bus (DQ<15:0>) is not synchronized with the common clock signal (CK), instead a standalone bidirectional data strobe (DQS) is used to sync the data bus. Actually the x16 version of the ram (the one I'm using) has 2 data strobes, LDQS for the lower byte of data (DQ<7:0>) and UDQS for the upper byte of data (DQ<15:8>).
The following is taken from page 98 of the previously mentioned datasheet and it illustrates the data valid windows:
**broken link removed**
Now, I can't use a DQS signal as-it-is to sample data since its edges are not centered with data, a shift of about 90 degrees would be necessary. Unfortunately DQS is not free-running, therefore a DCM can't be used to provide the required phase shift.
I've searched on the network for some examples, and as far as I can see no one actually uses the DQS signals to read data from the RAM, instead they uses a properly shifted version of the internal FPGA clock (the same that goes on the CK line of the RAM).
The required shift really depends on the application, for example one board could have longer data tracks than another, hence the skew difference that requires the FPGA to shift the clock of a different value.
Would be measuring the timings on field and hard-coding a shift value in the FPGA bad practice?
Besides the manually shifted clock solution (which sounds quite horrible, but you tell me) I have no idea on how to accomplish this, any suggestion will be really appreciated.
Thanks.
The memory is a single 512Mb chip by Micron (32M x 16, that is the data bus is 16 bits wide), and the following is its datasheet: https://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf
Writing the RAM is quite straightforward, but reading it is giving me nightmares.
The DDR2 uses a source synchronous interface, that is the data on the parallel data bus (DQ<15:0>) is not synchronized with the common clock signal (CK), instead a standalone bidirectional data strobe (DQS) is used to sync the data bus. Actually the x16 version of the ram (the one I'm using) has 2 data strobes, LDQS for the lower byte of data (DQ<7:0>) and UDQS for the upper byte of data (DQ<15:8>).
The following is taken from page 98 of the previously mentioned datasheet and it illustrates the data valid windows:
**broken link removed**
Now, I can't use a DQS signal as-it-is to sample data since its edges are not centered with data, a shift of about 90 degrees would be necessary. Unfortunately DQS is not free-running, therefore a DCM can't be used to provide the required phase shift.
I've searched on the network for some examples, and as far as I can see no one actually uses the DQS signals to read data from the RAM, instead they uses a properly shifted version of the internal FPGA clock (the same that goes on the CK line of the RAM).
The required shift really depends on the application, for example one board could have longer data tracks than another, hence the skew difference that requires the FPGA to shift the clock of a different value.
Would be measuring the timings on field and hard-coding a shift value in the FPGA bad practice?
Besides the manually shifted clock solution (which sounds quite horrible, but you tell me) I have no idea on how to accomplish this, any suggestion will be really appreciated.
Thanks.