Designing a cascade SD modulator

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raceon1600

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cascade

Dear all,
I want to simulate a cascaded SD modulator in Hspice, but I dont have any idea how to extract the first stage quantization noise and feed it to the next stage.
Does anyone have a paper or an article that would help me?
Thanks.
 

refer to richard shreier's book on "understanding delta sigma converters". It's detailed in there.
 

Would you please tell me which pages I must study? I couldnt find the issue in that book!!!
 

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