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Designing 3 a stage opamp

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suria3

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3-stage op amp

Hi,

I'm designing a 3 stage opamp. The 1st stage is the NMOS differential amplifier, 2nd stage PMOS gain stage and the 3rd stage is PMOS gain stage is well. I have have the gain of 90dB. But the circuit of course not stable as the PM is just 15 deg. I have just done the pole-zero compensation from the 2nd stage output to the 1st stage. So, can you guys guide me what is the proper way of compensation for 3 stage opamp design, is there any good papers available, please pass it here.

Thanks in advance,
Suria
 

c_m_o_s

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what is the architecture of each stage ? what's your load capacitance ? where is your dominant pole coming from ..i mean which stage ?and where are the poles located wrt each other ?
 

suria3

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c_m_o_s said:
what is the architecture of each stage ? what's your load capacitance ? where is your dominant pole coming from ..i mean which stage ?and where are the poles located wrt each other ?
As i said, the 1st stage is the NMOS input differential stage, 2nd stage is the common drain PMOS and 3rd also the common drain PMOS gain stage. The load is approximately 50pF and i believe the dominant pole is from the 3rd stage output. The poles location according to the transfer function is on the left plane.
 

c_m_o_s

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what i meant by asking about architecture was whether you are going for cascode structure at any stage (which would have increased the impedance at that node causing more trouble)...anyways, your Cl is 50 pF so your dominant pole is most likely at the third stage output...can you tell me what is the need for three stages..i believe you can get 90dB from even two stages. Also is the third stage pmos very big in size ?

And what is your GBW requirement ?
 

suria3

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c_m_o_s said:
what i meant by asking about architecture was whether you are going for cascode structure at any stage (which would have increased the impedance at that node causing more trouble)...anyways, your Cl is 50 pF so your dominant pole is most likely at the third stage output...can you tell me what is the need for three stages..i believe you can get 90dB from even two stages. Also is the third stage pmos very big in size ?

And what is your GBW requirement ?
All the gain stages are the simple common source configuration without cascode design. Since the power supply is 1.8V, i wont be able to design cascode stage. I need such a large gain for a error-amplifier application in the offset cancellation circuit. The pmos is large size, thus to contribute high gm to increase output impedance. Do you think cascode stage is fine for 1.8V power supply, if yes what type of cascode, i believe telescopic is not possible coz it will limit the output swing.

I need a low GBW since the opamp will be applied at low feedback system.
 

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