Why do I get the sense that you are posting your homework questions here?Data is coming with width 44 bits with a valid signal to a block as input. The block needs to send this incoming data as output of this block with data width of 60 bits and with a output valid signal for the output data. Can you please design this?
Sure if you forward your first born and year's salaryData is coming with width 44 bits with a valid signal to a block as input. The block needs to send this incoming data as output of this block with data width of 60 bits and with a output valid signal for the output data. Can you please design this?
The input data can come to the block in every clock cycle as continuous valid data of 44 bits each.The datapath of a clocked design has 1 to N clock cycles latency, the data valid signal has to be delayed by the same number of clock cycles.
Presume you mean "combined" rather than "added" here.Then, the remaining 44-16=28 bits of the second input of 44 bits are added with 32 bits of the third input data of 44 bits and send as the second output of the block with a valid signal.
The input data can come to the block in every clock cycle as continuous valid data of 44 bits each.The datapath of a clocked design has 1 to N clock cycles latency, the data valid signal has to be delayed by the same number of clock cycles.
Presume you mean "combined" rather than "added" here.
How to decide that after 15 inputs packets same thing repeats? Are you following and Lowest common multiple (LCM) or highest common factor (HCF) approach?It's essentially a reasssembly of data bits. You'll get 11 output packets for 15 input packets. The output datavalid rate will be respectively 11/15 of the input rate.
Do you want to mean that state for y(0), y(1), y(2), y(3) will not have any output and output start coming for states with outputs y(4) to y(14)?There are different ways to set up the design. You can e.g. make a FSM with 15 states advanced , each representing y( n) as a specific combination of x( n), x(n-1) and x(n-2), including 4 states that generate no new output.
Where in post#10 it is mentioned that we need storage registers for x(n-1) and x(n-2)?Need storage registers for x(n-1) and x(n-2), already mentioned in post #10.
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