Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Design Shifter_Register/ Error "default binding for component instance"

Status
Not open for further replies.

tri2061990

Newbie level 5
Joined
May 20, 2011
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,366
This is shift_reg code

library ieee ;
use ieee.std_logic_1164.all;

---------------------------------------------------

entity shift_reg is
port(
Din :in std_logic_vector(7 downto 0);
clock: in std_logic;
shift_enable: in std_logic;
Dout: out std_logic_vector(7 downto 0)
);
end shift_reg;

---------------------------------------------------

architecture behv of shift_reg is

-- initialize the declared signal

signal S:std_logic_vector(7 downto 0);
signal a:std_logic;
begin
a<=Din(7);

process(clock, shift_enable, Din)
begin

-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift_enable = '1' then
S <= a & Din(7 downto 1);
else S<=Din;
end if;
end if;

end process;

-- concurrent assignment
Dout <= S;

end behv;


This is test code
library ieee;
use IEEE.Std_logic_1164.all;
use IEEE.Std_logic_arith.all;

entity test_shifter_reg is
end test_shifter_reg;

architecture behv of test_shifter_reg is

signal Din:std_logic_vector(7 downto 0);
signal clock:std_logic:='0';
signal shift_enable:std_logic;
signal Dout:std_logic_vector(7 downto 0);

component shifter_reg is
port(
Din : in std_logic_vector(7 downto 0);
clock: in std_logic;
shift_enable: in std_logic;
Dout: out std_logic_vector(7 downto 0)
);
end component;

begin
create_clock:process
begin
wait for 15 ns;
clock<=not clock after 50 ns;
end process create_clock;

create_data:process
begin
Din<="10001100";
shift_enable<='0';
wait for 10 ns;

shift_enable<='1';
wait for 100 ns;
shift_enable<='0';
wait;
end process create_data;

DUT:component shifter_reg
port map(Din=>Din,clock=>clock,shift_enable=>shift_enable,Dout=>Dout);

end behv;



Error
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: test_shifter_reg.vhd(44): Bad default binding for component instance "dut : shifter_reg".
# (Component port "clock" is not on the entity.)
# ** Warning: [1] test_shifter_reg.vhd(44): (vopt-3473) Component instance "dut : shifter_reg" is not bound.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 6

Help me,please.I use Model Sim SE plus 6.3f
 

dcreddy1980

Full Member level 5
Joined
Dec 3, 2004
Messages
243
Helped
46
Reputation
92
Reaction score
21
Trophy points
1,298
Location
Munich, Germany
Activity points
1,532
Looking at first glance...your entity name is "shift_reg" and the component is "shifter_reg".
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top