design rule violations

[cyrax747]

Hi All,

In my design of 45nm,Finally after routing i got ~70 max fanout violations in soc encounter.When i tried ti fix using ecorepeater and ecosizecell commands my max fanout violations increased,to my surprise 5 max tran violations popped out in setup mode.

So i have fixed those max tran violations and finally there are only max fanout violations > 100 .My doubt is if i fix fanout ,tran violations are popped out and vice versa putting me in loop.How to balance the both and fix all the violations.

 

[rca]

Why do you need to close the fanout violation?
The timing table (liberty file) have two axis, one is the load (cap) and the second the input transition, so the fanout is not included and only as indication to be a weak point, but if you have enough margin on the path which have this fanout violation you could ignore them, except the liberty view table are dependent of the fanout, I don't expect.