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Design rule constraints - they are max_capacitance, max_transition etc - usually they come with std. cell library or with IP library (from IP vendor, not the EDA vendor). And user may override them for his design.
Another DRC is Design Rule Check for layout (min width of wires, spacing between of polygons etc). They come from foundry. User can not modify them without permission from foundry.
Design rule constraints - they are max_capacitance, max_transition etc - usually they come with std. cell library or with IP library (from IP vendor, not the EDA vendor). And user may override them for his design.
Another DRC is Design Rule Check for layout (min width of wires, spacing between of polygons etc). They come from foundry. User can not modify them without permission from foundry.
You can modify the rules to bypass some violations that you are sure to fix in later stages of the design. If you mask off violations and tape out the design, foundry will send it back for fixing, since the design goes through another set of DRC checks at foundry.
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