design rule constraint

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Hi, everyone:
I‘m a newer of Design Compile. When I read the design rule constraint section of <Design Compile User Guide>. I found a design rule constraint called minimum capacitance. I know that the maximum capacitance constraint could be used to limit the transition time and something similarly. But i don't know why the DC or library has the minimum capacitance constraint. Similarly, the minimum transition time constraint. Could anyone explain it for me. Thanks in advance~
 
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I think the minimum cap due to the internal cap of the cell. Even if the load is zero there will be a cap practically.
And i guess the min transition is for the cell to recognise the signal as a valid input signal.
 

DC User Guide says that: "The min_capacitance design rule specifies the minimum load a cell can drive. It specifies
the lower bound of the range of loads with which a cell has been characterized to operate.
During optimization."
So, the minimum capacitance may be not the internal capacitance of the cell.
And set_min_capacitance command can only be used for input or inout ports; you cannot set minimum capacitance on a design.

---------- Post added at 15:03 ---------- Previous post was at 15:00 ----------
pavanks said:
I think the minimum cap due to the internal cap of the cell. Even if the load is zero there will be a cap practically.
And i guess the min transition is for the cell to recognise the signal as a valid input signal.
Click to expand...
 

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